1. Field of the Invention
The present invention relates to a structure of a gate electrode, and more particularly to a technique for forming a gate structure in which a silicide layer is stacked on a polysilicon layer.
2. Description of the Background Art
Conventionally, polycrystalline silicon (polysilicon) has been widely used as a material for a portion which should be resistant to heat, such as a gate electrode of a MOS transistor or a wire at a lower level of a multi-level interconnect structure.
In recent years, a semiconductor device has been further miniaturized, as well as an operation speed thereof has been further increased, to require reduction of a resistance and narrowing of a gate electrode (reduction of a gate length) of a MOS transistor. One known technique to meet with the foregoing requirement is siliciding of an upper portion of a gate electrode formed using polysilicon, which provides for reduction of a resistance of the gate electrode. Thus, a gate electrode has typically a structure where a silicide layer is formed on a polysilicon layer.
FIG. 28 is a copy of a photograph of a section of a MOS transistor in a conventional semiconductor device, which is taken along a direction of a channel length of the MOS transistor. FIG. 29 is a diagrammatical illustration of FIG. 28. Below, a structure of the conventional semiconductor device will be described with reference to those figures.
A gate insulating film 3 and a gate electrode 4 are formed on a well 2 which has a polarity of either a p-type or an n-type and is formed in a silicon substrate 1. The gate electrode 4 is formed of polysilicon with an upper portion thereof being silicided. In other words, the gate electrode 4 includes a polysilicon layer 4a and a silicide layer 4b formed on the polysilicon layer 4a. Further, a sidewall 5 is formed on a side face of the gate electrode 4. Moreover, source/drain regions 6 each having a polarity reverse to that of the well 2 are formed in the well 2 on opposite sides of the gate electrode 4. Each of the source/drain regions 6 has a two-part structure composed of a relatively shallow source/drain extension layer 6a and a relatively deep source/drain diffusion layer 6b. A surface portion of each of the source/drain regions 6 is silicided so that a silicide layer 6c is formed in a corresponding portion.
Siliciding of a polysilicon gate electrode of a MOS transistor is typically formed by the following steps. First, a gate electrode and source/drain regions are formed on a silicon substrate, directly on which a metal film is then formed. Next, annealing is carried out to cause a metal in the metal film and silicon in the gate electrode and the source/drain region to react with each other. As a result, a silicide layer is formed in a self-aligned manner in an upper portion of each of the gate electrode and the source/drain regions. The foregoing steps are collectively known as a salicide (self-aligned-silicide) process.
As generally known, when a metal and silicon are caused to react with each other to form silicide as in a salicide process described above, a volume of the silicide formed as a result of the reaction between the metal and the silicon is smaller than a total volume of the metal and the silicide before the reaction. Accordingly, the silicide as formed should suffer a great stress.
Thus, when narrowing of a polysilicon gate electrode (reduction of a gate length) is further advanced to such an extent that the width of the gate electrode is substantially equal to a grain size of silicide, use of siliciding results in agglomeration of silicide to be formed, to possibly cause disconnection. As a result, a wire resistance is significantly increased to invite signal delay. Signal delay is a detrimental to increase in an operation speed of a semiconductor device, and degrades an operational reliability. In fact, as narrowing of a gate electrode is further advanced, it becomes more difficult to rely on siliciding of an upper portion of the gate electrode to achieve reduction of a resistance.
In accordance with conventional practices to overcome the above-described problem, a polysilicon gate electrode is formed such that a size of an upper portion thereof (i.e., a portion in which silicide is formed) is increased. Such structure makes it possible to reduce a gate length of a transistor, while preventing agglomeration of silicide in the gate electrode to reduce a resistance. Known examples of the gate electrode having the foregoing structure include a notched gate electrode, a T-shaped gate electrode and an inverted-trapezoid-shaped gate electrode.
A notched gate electrode is as described by T. Ghani et al. in an article entitled xe2x80x9c100 nm Gate Length High Performance/Low Power CMOS Transistor Structurexe2x80x9d IEDM Technology Digest, IEEE, 1999, pp. 143, for example. A T-shaped gate electrode is as described by C.-P. Chao et al. in an article entitled xe2x80x9cLow Resistance Ti or Co Salicided Raised Source/Drain Transistors for Sub-0.13 xcexcm CMOS Technologiesxe2x80x9d IEDM Technology Digest, IEEE, 1997, pp. 103, for example. An inverted-trapezoid-shaped gate electrode is as described in Japanese Patent Application Laid-Open No. 4-215441 on pages 3 through 5 and FIGS. 1 through 5B, for example.
However, the above-cited known structures for gate electrodes have disadvantages. With respect to a notched gate electrode, which is intended to reduce a gate length by forming a notch in a bottom corner of a gate electrode, it is technically difficult to steadily form a gate electrode with a notch at a bottom corner thereof, and thus is not suitable for mass production.
A T-shaped gate electrode is intended to reduce a resistance of a gate electrode by forming a polysilicon layer wider than a gate electrode on the gate electrode. To form a T-shaped gate electrode requires use of a process for forming a raised source/drain structure which involves selective epitaxial growth. It is also technically difficult to carry out such a process which involves selective epitaxial growth, in view of non-establishment of a standardized method of measuring a thickness of a grown film, incompleteness of selectivity or the like.
Then, an inverted-trapezoid-shaped gate electrode is intended to reduce a resistance of a gate electrode by forming a gate electrode such that a vertical section thereof taken along a direction of a channel length has a shape of an inverted trapezoid. To form a gate electrode so as to have a shape of an inverted trapezoid in vertical section requires a damascene process or the like, to necessitate substantial modification to a conventional manufacturing process.
It is an object of the present invention to provide a semiconductor device which can be formed easily and provides for reduction of a gate length and a resistance of a gate electrode in a MOS transistor, and to provide a manufacturing method thereof.
According to a first aspect of the present invention, a semiconductor device includes the steps (a) to (e). The step (a) is to form a gate insulating film on a semiconductor substrate and forming polysilicon on the gate insulating film. The step (b) is to implant ions into the polysilicon. The step (c) is patterning of the polysilicon to form a gate electrode. The step (d) is to anneal the gate electrode. The step (e) is siliciding of an upper portion of the gate electrode. A total dose of the ions to be implanted in the step (b) is 6xc3x971015/cm2 or larger.
The annealing process in the step (d) causes an upper portion of the gate electrode to expand. For this reason, even when the width of the gate electrode is reduced for the purpose of reducing a gate length, agglomeration of silicide formed in the upper portion of the gate electrode in the step (e) can be prevented. Thus, it is possible to reduce both the gate length and a resistance of the gate electrode of a MOS transistor. This contributes to increase in an operation speed and improvement in operational reliability of the semiconductor device. Further, the semiconductor device can be formed without having to use a technically difficult process.
A second aspect of the present invention is intended for a method of manufacturing a semiconductor device including a p-channel MOS transistor and an n-channel MOS transistor. According to the third aspect of the present invention, the method includes the steps (a) to (g). The step (a) is to form a gate insulating film on a semiconductor substrate, and form polysilicon on the gate insulating film. The step (b) is to implant phosphorus ions into an entire surface of the polysilicon except a region where the p-channel MOS transistor is to be formed. The step (c) is patterning of the polysilicon to form respective gate electrodes of the p-channel MOS transistor and the n-channel MOS transistor. The step (c) is performed after the step (b). The step (d) is to form a source/drain region of the n-channel MOS transistor in the semiconductor substrate by ion implantation using the gate electrode of the n-channel MOS transistor as a mask. The step (e) is to form a source/drain region of the p-channel MOS transistor in the semiconductor substrate by another ion implantation using the gate electrode of the p-channel MOS transistor as a mask. The step (f) is to anneal the respective gate electrodes of the p-channel MOS transistor and the n-channel MOS transistor. The step (g) is siliciding of an upper portion of each of the respective gate electrodes of the p-channel MOS transistor and the n-channel MOS transistor. A total dose of ions implanted in the steps (b) and (d) is 6xc3x971015/cm2 or larger.
The annealing process in the step (f) causes an upper portion of the gate electrode to expand. For this reason, even when the width of the gate electrode is reduced for the purpose of reducing a gate length, agglomeration of silicide formed in the upper portion of the gate electrode in the step (g) can be prevented. Further, as the phosphorus ions are typical n-type dopants and each have a relatively large mass number, the use of the phosphorus ions contributes to facilitation of the method of manufacturing a semiconductor device according to the present invention, and allows the upper portion of the gate electrode to efficiently expand. Moreover, by implanting the phosphorus ions at a high concentration into the polysilicon of the gate electrode of the n-channel MOS transistor, it is possible to suppress depletion of the gate electrode, which results in improvement in a current drive capability.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.